SMH4814 Datasheet, PDF (15/44 Pages) Summit Microelectronics, Inc. – Dual Feed Active-ORing Programmable Hot Swap Controller

APPLICATIONS INFORMATION (CONTINUED)
SMH4814
Preliminary Information
The SMH4814 provides three methods for controlling
inrush current. The first method entails limiting the
current being sourced from the VGATE_HS pin. The
maximum current out of this pin (I_{VGHS_MAX}) is a
programmable value from 8ua to 128µa (nominal),
based on register R0E[3:0]. The importance of having
a current-limited gate drive is that the slew rate of the
load voltage is roughly equivalent to the slew rate of
the FET gate to drain capacitance, once the gate to
source potential has reached the FET’s threshold
voltage. This slew rate (computed by dividing the gate
current by the gate-drain capacitance) may be easily
modified by adjusting the gate-drain capacitance,
which may be a discrete component or capacitance
built into the FET structure, or by adjusting the gate
current.
A second tool for limiting inrush current is based on
further controlling the current being sourced from
VGATE_HS. The SLEW_CNTL pin may be used to
cause the gate current to linearly ramp from 0µA to the
maximum amount (described above) in the following
manner. On power-up, SLEW_CNTL is clamped at
VSS; when VGATE_HS is enabled, SLEW_CNTL
outputs 5µA drawn from the internal 5V supply. If bit 4
of register R0E is set high, then the current out of
VGATE_HS is reduced by the ratio of the voltage on
SLEW_CNTL divided by 2.5V. Once SLEW_CNTL
exceeds 2.5V, then the current is limited to I_{VGHS_MAX}.
The advantage of ramping the gate current from zero
up to its maximum amount is that the corresponding
inrush current will follow a similar pattern, which may
lead to less disruption to the overall system. The rate
at which the gate current increases is determined by
the size of the external capacitor connected to the
SLEW_CNTL pin.
The third method for controlling inrush current is based
on the SMH4814’s Current Regulation feature.
Described in more detail in a later section, this feature
regulates the current through the FET, and therefore
the voltage across an external sense resistor as
measured by the CBSENSE input, by controlling
VGATE_HS. Normally, this operation attempts to
keep CBSENSE from exceeding a programmable
threshold voltage, V_CR; however, when the load is
being initially powered, the regulation point at which
CBSENSE is held may be gradually ramped from zero
up to V_CR. This feature is enabled by setting bit 5 of
register R0E high, and by selecting a ratio using
R0E[7:6].
In this case, CBENSE is regulated to the voltage on
SLEW_CNTL times the ratio determined by R0E, up to
the value of V_CR.
The methods described here for controlling inrush
current may be used separately or together. Once the
voltage on SLEW_CNTL is within a p-ch threshold
voltage of 5V_CAP, it must remain above this voltage.
Load Control — Sequencing the Secondary
Supplies
The PUP_A through PUP_D output pins are used to
enable the external DC/DC controllers. Once the load
has been fully powered, PUP sequencing may begin.
The SMH4814 checks that two conditions have been
met to indicate that the load is fully powered:
1) DRAIN SENSE input voltage must be < 2.5V
And
2) VGATE_HS voltage must be > V₁₂ – V_GT.
The DRAIN SENSE input helps ensure that the power
MOSFET is not absorbing excessive steady state
power from operating at a high V_DS. This sensor
remains active at all times (except when current
regulation is enabled). The VGATE sensor makes sure
that the power MOSFET is operating well into its
saturation region before allowing the loads to be
switched on. Once VGATE reaches V₁₂ – V_GT this
sensor is latched.
PUP Outputs
The SMH4814 has four programmable-polarity, open-
drain PUP (Power-Up Permitted) outputs that may be
used to control the sequencing order of DC-DC
converters. After the soft start process has been
completed and the load capacitance has been fully
charged, there are four sequential time slots into which
each of the PUP outputs may be assigned (Figure 5).
A given time slot may have more than one PUP output
assigned to it; likewise, a time slot may have no PUP
outputs assigned to it. Time Slot 0 begins after the
gate of the main soft-start FET is fully enhanced and
the load is fully charged.
Summit Microelectronics, Inc
2080 2.0 07/21/05
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