RM0319 Datasheet, PDF (94/368 Pages) STMicroelectronics – SPEAr320S architecture and functionality

Serial NOR Flash controller (SMI)
7.3
Functional description
Figure 21 shows the block diagram of SMI.
SMI consists of two main interfaces:
● The clock prescaler (Section 7.3.1)
● The data processing and control (Section 7.3.2)
Figure 21. SMI block diagram
SMI Clock
Prescaler
(1 to 127)
SMI Data processing
and Control
Transmit Register
AHB Slave
Interface
Control and
Status Register
RM0319
Clock
Data,
command
Bank select
SPI-
Compatible
Memories
Receive Register/
Status Regsiter
Data,
Status
7.3.1
7.3.2
Clock prescaler
The SMI clock prescaler block allows to set up the memory clock SMI_CLK using the AHB
clock HCLK, as detailed in Section 7.4.
Data processing and control
The SMI data processing and control block represents the logic controlling the transfer of
data between SPI-compatible off-chip memory and AHB bus. Transfer rules through both
AHB-to-SMI and SMI-to-memory interfaces. The different data transfer modes between SPI-
compatible off-chip memory and AHB bus are detailed in Section 7.3.4.
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