RM0319 Datasheet, PDF (323/368 Pages) STMicroelectronics – SPEAr320S architecture and functionality

RM0319
Power, reset and clock control
Table 116. Power state for asynchronous DRAM system (DRAM clocked by PLL2)
State
ARM
ARM clock
DRAM
Possible code
execution memory
SLOW
Running
NORMAL Running
MAIN Osc. (PLL off)
MAIN Osc.(PLL off)
PLL1 (Up to 333 MHz)
Self refresh
Active
Active
Internal memory
Internal memory and
external DRAM
Internal memory and
exernal DRAM
30.1.1
Note:
30.1.2
SLEEP
During this mode the system clocks, HCLK and CLK, are disabled and the system controller
clock SCLK is driven from a low speed oscillator (nominally 32 768 Hz). When either a FIQ
or an IRQ interrupt is activated (through the VIC) the system moves into the DOZE mode.
Additionally, the required operating mode in the system control register automatically
changes from SLEEP to DOZE.
In SLEEP state, the clock is not provided to CPU. This state maximizes power saving.
The system controller clock is driven by the last selected source in DOZE mode, it could be
RTC or main oscillator.
On interrupt request, normal (IRQ) or fast (FIQ) request, the CPU wakes up and goes in
DOZE. Few clock cycles (less than five) are required for this transition.
To reduce power consumption, it is recommended to switch off all clocks to modules which
are not used for wake-up purpose (see Section 30.4: Reset).
Interrupts enabling wake-up from SLEEP state are:
● Ethernet MAC: It is possible to disable the clock to Ethernet MAC
(PERIP1_CLK_ENB.gmac_clkenb) using the external clock provided by PHY MAC.
● USB Device: In this case, the clock to USB Device cannot be switched off
(PERIP1_CLK_ENB.usbdev_clkenb) and AHB since the resume interrupt is registered
by HCLK.
● RTC: All clocks to internal modules can be switched off (except for RTC).
● GPIO: All clocks to internal modules can be switched off (except for GPIO).
● TIMER: All timers if timer clock is not switched off (see PERIP1_CLK_ENB register for
timer clock sources)
Sleep state is only activated if SCCTRL Mode Ctrl is set to zero and processor is in Wait-for-
Interrupt state.
DOZE (reset state)
DOZE is the first state activated after reset.
During this mode the system clocks, HCLK and CLK, and the system controller clock SCLK
are driven from the output of crystal oscillator (24 MHz) or low frequency oscillator (32 kHz).
The system controller moves into SLEEP mode from DOZE mode only when none of the
mode control bits are set and the processor is in Wait-for-interrupt state. If SLOW mode or
NORMAL mode is required the system moves into the XTAL control transition state to
initialize the crystal oscillator.
Doc ID 022640 Rev 3
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