RM0319 Datasheet, PDF (1/368 Pages) STMicroelectronics – SPEAr320S architecture and functionality

RM0319
Reference manual
SPEAr320S architecture and functionality
Introduction
The SPEAr320S is a member of the SPEAr3xx family (includes SPEAr320S, SPEAR320,
SPEAr310 and SPEAr300).
SPEAr3xx devices all feature ARM926EJ-S core running up to 333 MHz, an external DDR2
memory interface, a common set of powerful on-chip peripherals. Each member of the
SPEAr3xx family has a specific set of IPs implemented in its reconfigurable array subsystem
(RAS).
This document provides technical details about the architecture and functionality of
SPEAr320S, and is intended to be used by system-level and board-level product designers,
as well as software developers.
The SPEAr320S address map and detailed register descriptions are provided in a separate
reference manual: RM0321: SPEAr320S address map and registers.
For the pin out, ordering information, mechanical, electrical and timing characteristics,
please refer to the SPEAr320S datasheet.
November 2012
Doc ID 022640 Rev 3
1/368
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