8169 Datasheet, PDF (9/30 Pages) STMicroelectronics – DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX™

STA304A
4.0 I2S OUTPUT INTERFACE CONFIGURATION
In order to configure the I2S output interface the Configuration Register B (CRB) can be used. Using the 3
I2SO_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of
them.
MODE # of SLOTS W. LENGHT
ALIGNMENT
DELAY SLOT
NOTES
0
32
24
Left
No
1
32
24
Left
Yes
2
32
16
Right
No
MSb first only
3
32
24
Right
No
4
24
24
Left
No
Slave only
5
Not valid
Not valid
Not valid
Not valid
Reserved, do not use.
6
24
16
Right
No
MSb first only. Slave only
7
24
24
Right
No
Slave only
By default standard I2S output interface master is provided (mode 1 in bits 8,9,10 of register CRB,
I2SO_BICK_Pol = 1 and I2SO_LRCK_Pol = 0 in the same register)
4.1 Switching characteristics (10 pf load; Fsm=48 KHz):
SCKO frequency (master mode):
64 Fsm
(slave mode):
64 Fsm
SCKO pulse width low (T₀) (slave mode):
min 40 ns.
SCKO pulse width high (T₁) (slave mode):
min 40 ns.
SCKO active to LRCKO edge delay (T₂):
min 20 ns.
SCKO active to LRCKO edge setup (T₃):
min 20 ns.
SDO valid to SCKO active setup (T₄):
min 20 ns.
SCKO active to SDO hold time (T₅):
min 20 ns.
SCKO falling to LRCKO edge (T₆) (master mode):
min 2 ns; max 8 ns.
SCKO falling to SDO edge(T₇) (master mode):
min 2 ns; max 8 ns.
(slave mode):
min 6 ns; max 17 ns
Figure 3.
T₂
T₃
LRCKO
BICKO
SDO
T₆
T₄
T₁
T₀
T₇
T₅
D00AU1245
9/30