8169 Datasheet, PDF(11/30 Page) STMicroelectronics – DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX™

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8169 Datasheet, PDF (11/30 Pages) STMicroelectronics – DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX™

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STA304A

6.0 DAP INPUT STAGE

The device provides 3 mutually exclusive input interfaces: I2S, S/PDIF and AC`97. Hereby is a small description

of the characteristics for each of them and a table showing how to select it.

Figure 6.

I2S

S/PDIF

AC97

I2S_SPDIF_Sel

LRCK

SRC

AC97_Sel

PLL_Factor

PLL

PLL_Bypass

XTI

I2C

SRC_Bypass

YRAM

LEFT

RIGHT

SL/CENTER

CENTER

LFE

DSP

YRAM

LEFT

RIGHT

SL/CENTER

CENTER

LFE

MCK

/1024

LRCK

/2 or /8 CK_OUT

DDX

I2S

6.1 Input from I2S

Using this input interface a maximum of 4 channels can be sent to the DSP. As detailed in the related paragraph

this I/F can be configured both as master or slave. When in master the sampling frequency is fixed to 48 KHz

and the SRC can be bypassed using the SRC_Bypass configuration bit (in CRA register). If slave operation is

selected the full range between 32KHz and 96KHz is supported but the SRC must always be in the processing

path (no bypass). In order to select this interface the AC97_MODE pin must be tied to GND and the

I2S_SPDIF_Sel bit must be 0.

6.2 Input from S/PDIF

This interface is compliant with the AES/EBU IEC 958, S/PDIF and EIAJ CP-340/1201 professional and con-

sumer standards. The full range from 32 KHz up to 96 KHz is supported but the SRC bypass option must be

switched off. Using the SPDIF_Mode bit this interface can be configured as digital or analog input. If the analog

mode is selected the line receiver can decode differential as well as single ended inputs. The receiver consists

of a differential input Schmitt Trigger comparator with 50 mV of hysteresis, which prevents noisy signals from

corrupting the data recovered. The minimum input differential voltage is 200 mV.

If the digital mode is selected only the single ended operation is supported; the input signal should be CMOS

compliant.

In order to select this interface the AC97_MODE pin must be tied to GND and the I2S_SPDIF_Sel must be 1.

6.3 Input from AC`97

In order to select this interface the AC97_MODE pin must be tied to VDD (I2S_SPDIF_Sel bit âis donât care).

The AC`97 interface can be configured either as primary or secondary device using the external configuration

pin SA.

This interface support 4 sampling frequencies, according to the Variable and Double Rate Audio Codec `97

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