8169 Datasheet, PDF (8/30 Pages) STMicroelectronics – DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX™

STA304A
3.0 I2S INPUT INTERFACE CONFIGURATION
In order to configure the I2S input interface the Configuration Register B (CRB) can be used. Using the 3
I2SI_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of them.
MODE # of SLOTS W. LENGHT
ALIGNMENT
DELAY SLOT
NOTES
0
32
24
Left
No
1
32
24
Left
Yes
2
32
16
Right
No
MSb first only
3
32
24
Right
No
4
24
24
Left
No
Slave only
5
Not valid
Not valid
Not valid
Not valid
Reserved, do not use.
6
24
16
Right
No
MSb first only. Slave only
7
24
24
Right
No
Slave only
By default standard I2S input interface slave is provided (mode 1 in bits 0,1,2 of register CRB, I²S_BICK_Pol = 1 and
I2SI_LRCK_Pol = 0 with some register)
3.1 Switching characteristics (10 pf load; Fsm=32 KHz to 96KHz):
BICKI frequency (master mode):
3.072MHz
(slave mode):
Max 6.4 MHz
BICKI pulse width low (T₀) (slave mode):
min 40 ns.
BICKI pulse width high (T₁) (slave mode):
min 40 ns.
BICKI active to LRCKI edge delay (T₂):
min 20 ns.
BICKI active to LRCKI edge setup (T₃):
min 20 ns.
SDI valid to BICKI active setup (T₄):
min 20 ns.
BICKI active to SDI hold time (T₅):
min 20 ns.
BICKI falling to LRCKI edge (T₆) (master mode): min 3 ns; max 9 ns.
Figure 2.
T₂
T₃
LRCKI
BICKI
SDI
T₆
T₄
T₁
T₀
D00AU1244
T₅
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