8169 Datasheet, PDF (18/30 Pages) STMicroelectronics – DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX™

STA304A
where CH stands for LR,SUR or SBW and x stands for the filter number (0..3).
The filter equation is Yn = Xn+((b0)-1)*Xn + 2*((b1)/2)*Xn-1 + b2*Xn-2 - 2*((a1)/2)*Yn-1 - a2*Yn-2 =
= b0*Xn + b1*Xn-1 + b2*Xn-2 - a1*Yn-1 - a2*Yn-2
The coefficient registers are 20 bits wide and should be in the range [-1..1) (80000h to 7ffffh).
Scaling factor registers:
For the filters Xn = - (-scale_in) * CHn , where CHn is the value before scaling and Xn is the input to the filter.
For the SBW redirection SBWn = -S (-scale_CH)*CHn
The scaling factor registers are 20 bits wide and should be in the range [-1..0] (80000h to 00000h).
SBW redirection: -1 for maximum redirection and 0 for no redirection.
Filter scaling: -1 for maximum input and 0 for no input to filter.
11.0 I²C BUS SPECIFICATION
The STA304A supports the I²C protocol. This protocol defines any device that sends data on to the bus as a
transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known
as the master and the others as the slave. The master always starts the transfer and provides the serial clock
for synchronisation. The STA304A is always a slave device in all its communications.
16bit registers are addressed as two 8 bit registers. The high byte has even address, while the low byte has odd
address. For example, reading from register 02 (16bit) means read registers 02 (HIGH BYTE) and 03 (LOW
BYTE) from I²C.
11.1 COMMUNICATION PROTOCOL
11.1.1Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high
are used to identify START or STOP condition.
11.1.2Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable
in the high state.A START condition must precede any command for data transfer.
11.1.3Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the
high state. A STOP condition terminates communications between STA304A and the bus master.
11.1.4Acknowledge bit
An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave,
releases the SDA bus after sending 8 bit of data.
During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of 8 bits of data.
11.1.5Data input
During the data input the STA304A samples the SDA signal on the rising edge of the clock SCL.
For correct device operation the SDA signal has to be stable during the rising edge of the clock and the data
can change only when the SCL line is low.
11.2 DEVICE ADDRESSING
To start communication between the master and the STA304A, the master must initiate with a start condition.
Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address
18/30