RM0366 Datasheet, PDF (76/868 Pages) STMicroelectronics – This reference manual targets application developers

RM0366
Power control (PWR)
Note:
6.1.3
When the RTC domain is supplied by V_DD (analog switch connected to V_DD), the following
functions are available:
• PC13, PC14 and PC15 can be used as GPIO pins
• PC13, PC14 and PC15 can be configured by RTC or LSE (refer to Section 24.3: RTC
functional description on page 596)
Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with
a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive
an LED).
When the RTC domain is supplied by V_BAT (analog switch connected to V_BAT because V_DD
is not present), the following functions are available:
• PC13, PC14 and PC15 can be controlled only by RTC or LSE (refer to Section 24.3:
RTC functional description on page 596)
Voltage regulator
The voltage regulator is always enabled after Reset. It works in three different modes
depending on the application modes.
• In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories
and digital peripherals).
• In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving
contents of registers and SRAM.
• In Standby Mode, the regulator is powered off. The contents of the registers and SRAM
are lost except for the Standby circuitry and the RTC Domain.
In the STM32F318x8 devices, the voltage regulator is bypassed and the microcontroller
must be powered from a nominal V_DD = 1.8 V ± 8% voltage.
6.2
6.2.1
Power supply supervisor
Power on reset (POR)/power down reset (PDR)
The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits
which are always active and ensure proper operation above a threshold of 2 V.
The device remains in Reset mode when the monitored supply voltage is below a specified
threshold, V_POR/PDR, without the need for an external reset circuit.
• The POR monitors only the V_DD supply voltage. During the startup phase V_DDA must
arrive first and be greater than or equal to V_DD.
• The PDR monitors both the V_DD and V_DDA supply voltages. However, if the application
is designed with V_DDA higher than or equal to V_DD, the V_DDA power supply supervisor
can be disabled (by programming a dedicated VDDA_MONITOR option bit) to reduce
the power consumption.
For more details on the power on /power down reset threshold, refer to the electrical
characteristics section in the datasheet.
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