RM0366 Datasheet, PDF (125/868 Pages) STMicroelectronics – This reference manual targets application developers

Reset and clock control (RCC)
RM0366
7.4.13
Clock configuration register 3 (RCC_CFGR3)
Address: 0x30
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res Res Res Res Res Res Res Res Res Res Res Res USART3SW[1:0 USART2SW[1:0]
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res
Res
TIM17
SW
Res
TIM16 TIM15
SW SW
Res
TIM1
SW
Res
I2C3 I2C2 I2C1
SW SW SW
Res
Res USART1SW[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:18 USART3SW[1:0]: USART3 clock source selection
This bit is set and cleared by software to select the USART3 clock source.
00: PCLK selected as USART3 clock source (default)
01: System clock (SYSCLK) selected as USART3 clock
10: LSE clock selected as USART3 clock
11: HSI clock selected as USART3 clock
Bits 17:16 USART2SW[1:0]: USART2 clock source selection
This bit is set and cleared by software to select the USART2 clock source.
00: PCLK selected as USART2 clock source (default)
01: System clock (SYSCLK) selected as USART2 clock
10: LSE clock selected as USART2 clock
11: HSI clock selected as USART2 clock
Bits 14:149 Reserved, must be kept at reset value.
Bit 13 TIM17SW: Timer17 clock source selection
Set and reset by software to select TIM17 clock source.
The bit is writable only when the following conditions occur: clock system = PLL, and AHB
and APB2 subsystem clock not divided respect the clock system.
The bit is reset by hardware when exiting from the previous condition (user must set the bit
again in case of a new switch is required)
0: PCLK2 clock (doubled frequency when prescaled) (default)
1: PLL vco output (running up to 144 MHz)
Bit 12 Reserved, must be kept at reset value.
Bit 11 TIM16SW: Timer16 clock source selection
Set and reset by software to select TIM16 clock source.
The bit is writable only when the following conditions occur: clock system = PLL, and AHB
and APB2 subsystem clock not divided respect the clock system.
The bit is reset by hardware when exiting from the previous condition (user must set the bit
again in case of a new switch is required)
0: PCLK2 clock (doubled frequency when prescaled) (default)
1: PLL vco output (running up to 144 MHz)
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