RM0366 Datasheet, PDF (573/868 Pages) STMicroelectronics – This reference manual targets application developers

Basic timers (TIM6)
Figure 236. Control circuit in normal mode, internal clock divided by 1
RM0366
,QWHUQDOFORFN
&(1 &17B(1
8*
&17B,1,7
&RXQWHUFORFN &.B&17 &.B36&
&RXQWHUUHJLVWHU

             
069
20.3.5
Debug mode
When the microcontroller enters the debug mode (Cortex^®-M4F core - halted), the TIMx
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. For more details, refer to Section 28.15.2: Debug
support for timers, watchdog and I2C.
20.4
TIM6 registers
Refer to Section 1.1 on page 35 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
20.4.1 TIM6 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UIF
Res Res Res Res RE- Res Res Res ARPE Res Res Res OPM URS UDIS CEN
MAP
rw
rw
rw
rw
rw
rw
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 UIFREMAP: UIF status bit remapping
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
Bit 10:8 Reserved, must be kept at reset value.
573/868
DocID025203 Rev 2