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STM8L052C6T6 Datasheet, PDF (65/102 Pages) STMicroelectronics – Value Line, 8-bit ultralow power MCU, 32-KB Flash, 256-byte data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC
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STM8L052C6
Electrical parameters
4. RTC enabled, LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
5. LCD enabled with internal LCD booster VLCD = 3 V , 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD
connected.
6. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 29.
7. RTC enabled. Clock source = LSE.
8. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after tWU.
9. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal
Symbol
Parameter
Condition(1)
Typ Unit
IDD(AH) (2)
Supply current in Active-halt
mode
VDD = 1.8 V
VDD = 3 V
VDD = 3.6 V
LSE
LSE/32(3)
LSE
LSE/32(3)
LSE
LSE/32(3)
1.15
1.05
1.30
µA
1.20
1.45
1.35
1. No floating I/O, unless otherwise specified.
2. Based on measurements on bench with 32.768 kHz external crystal oscillator.
3. RTC clock is LSE divided by 32.
In the following table, data is based on characterization results, unless otherwise specified.
Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V
Symbol
Parameter
Condition(1)
Typ
Max
IDD(Halt)
IDD(WUHalt)
tWU_HSI(Halt)(3)(4)
tWU_LSI(Halt) (3)(4)
Supply current in Halt mode
(Ultra-low-power ULP bit =1 in
the PWR_CSR2 register)
TA = -40 °C to 25 °C
TA = 55 °C
TA = 85 °C
Supply current during wakeup
time from Halt mode (using
HSI)
Wakeup time from Halt to Run
mode (using HSI)
Wakeup time from Halt mode
to Run mode (using LSI)
350
580
1160
2.4
1400(2)
2000
2800(2)
4.7
7
150
1. TA = -40 to 85 °C, no floating I/O, unless otherwise specified.
2. Tested in production.
3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
4. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after tWU.
Unit
nA
mA
µs
µs
Doc ID 023331 Rev 1
65/102
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