TDA7500 Datasheet, PDF (6/14 Pages) STMicroelectronics – DIGITAL AM/FM SIGNAL PROCESSOR

TDA7500
PIN DESCRIPTION (continued)
N°
NAME
TYPE
DESCRIPTION
58 CASALE
O DSP DRAM Column Address Strobe (Output). When in DRAM
Mode this pin acts as the column address strobe.
59 SDO<2>/SRA<17>/DSP1_GPIO<8 O
>
SAI Outputs (Output)/EMI SRAM Address Line<17>
(Output)/General Purpose I/O (Input/Output). One stereo channel
SAI data output in SAI mode. EMI address line 17 in SRAM Mode.
Optionally it can be used as a general purpose I/O.
60 SDO<2>/SRA<18>/DSP1_GPIO<7 O
>
SAI Outputs (Output)/EMI SRAM Address Line<18>
(Output)/General Purpose I/O (Input/Output). One stereo channel
SAI data output in SAI mode. EMI address line 18 in SRAM Mode.
Optionally it can be used as a general purpose I/O.
61 SDO<0>/SRA<19>
O SAI Output (Output)/EMI SRAM Address Line<19> (Output). One
stereo channel SAI data output in SAI mode. EMI address line 19
in SRAM Mode.
62 SDI<2>/SRA<20>/DSP1_GPIO<6> I
SAI Input (Input)/EMI SRAM Address Line<20> (Output)/General
Purpose I/O (Input/Output). One stereo channel SAI data input in
SAI mode. EMI address line 20 in SRAM Mode. Optionally it can
be used as a general purpose I/O.
63 SDI<1>/SRA<21>/RAS/DSP1_GPIO<5> I
SAI Input (Input)/EMI SRAM Address Line<21> (Output)/DRAM
Row Address Strobe (Output)/General Purpose I/O (Input/Output).
One stereo channel SAI data input in SAI mode. EMI address line
21 in SRAM Mode. When in DRAM Mode this pin acts as the row
address strobe. Optionally it can be used as a general purpose I/O.
64 SDI<0>/SRCCDC
I SAI Input (Input)/SPDIF Input 3 (Input). One stereo channel SAI
data input in SAI mode. Stereo SPDIF input intended to connect a
digital audio source like a CD changer in SPDIF mode.
65 SCKT
I/O SAI transmitter Bit Clock (Input/Output). SAI transmitter bit clock.
Master or slave.
66 LRCKT
I/O SAI transmitter Left-Right Clock (Input/Output). SAI transmitter
Left-Right clock. Can be master or slave mode.
67 SCKR
I/O SAI receiver Bit Clock (Input/Output). SAI receiver bit clock.
68 LRCKR
I/O SAI receiver Left-Right Clock (Input/Output). SAI receiver Left-
Right clock.
69 DBOUT1/DSP1_GPIO10
I/O Debug Port Serial Output (Input/Output)/ General Purpose I/O
(Input/Output). The serial data output for the Debug Port.
Optionally it can be used as a general purpose I/O.
70 DBIN1/OS10/DSP1_GPIO11
I/O Debug Port Serial Input/Chip Status 0 (Input/Output)/ General
Purpose I/O (Input/Output). The serial data input for the Debug
Port is provided when an input. When an output, together with
OS1 provides information about the chip status. Optionally it can
be used as a general purpose I/O.
71 DBCK1/OS11/DSP1_GPIO9
I/O Debug Port Bit Clock/Chip Status 1 (Input/Output)/General
Purpose I/O (Input/Output). The serial clock for the Debug Port is
provided when an input. When an output, together with OS0
provides information about the chip status. Optionally it can be
used as a general purpose I/O.
72 DBRQN1
I Debug Port Request Input (Input). Means of entering the Debug
mode of operation.
73 DBOUT0/DSP0_GPIO10
I/O Debug Port Serial Output (Input/Output)/ General Purpose I/O
(Input/Output). The serial data output for the Debug Port.
Optionally it can be used as a general purpose I/O.
74 DBIN0/OS00/DSP0_GPIO11
I/O Debug Port Serial Input/Chip Status 0 (Input/Output)/ General
Purpose I/O (Input/Output). The serial data input for the Debug
Port is provided when an input. When an output, together with
OS1 provides information about the chip status. Optionally it can
be used as a general purpose I/O.
6/14