TDA7500 Datasheet, PDF (2/14 Pages) STMicroelectronics – DIGITAL AM/FM SIGNAL PROCESSOR

TDA7500
path detection and one for sound processing. An
I2C/SPI interface is implemented for control and
communication with the main micro.
A separate SPI is available to interface the dis-
play micro.
The DSP cores are integrated with their associ-
ated data and program memories. The peripher-
als and interfaces I²C, SPI, Serial Audio Interface
(SAI), PLL Oscillator, External Memory Interface,
(EMI), General Purpose I/O register (Port A) and
the D/A registers are connected to and controlled
ABSOLUTE MAXIMUM RATINGS
by DSP0, whereas the A/D registers, the SPDIF
and the General Purpose I/O register (Port B) are
connected to and controlled by DSP1. The Debug
and Test Interface are connected to both DSP
cores.
The TDA7500 is supposed to be used in kit with
the TDA7501 or any other device of the same
family. Thanks to the serial audio interface also
digital sources can be processed and a direct
output to a digital bus is also available.
Symbol
VDD
VCC
T_amb
T_stg
Power supplies
Parameter
Analog Input Voltage
Digital Input Voltage
Operating Temperature Range
Storage Temperature
Digital
Analog
Warning: Operation at or beyond these limit may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Value
4.6
4.6
-0.5 to (VDD+0.5)
-0.5 to (VCC+0.5)
-40 to 85
-55 to 150
Unit
V
V
V
V
°C
°C
PIN CONNECTION
DSP0 GPIO0
DSP0 GPIO1
DSP0 GPIO2
DSP0 GPIO3
DSP0 GPIO4
DSP0 GPIO5
DSP0 GPIO6
DSP0 GPIO7
DSP1 GPIO4
DSP1 GPIO3
DSP1 GPIO2
DSP1 GPIO1
DSP1 GPIO0
TESTEN
TESTSE
NRESET
SCKM
MISOM
MOSIM
SSM
SCKD
MISOD
MOSID
SSD
AVDD
XTI
XTO
CLKIN
AGND
RDSINT
RDSARI_SCLK
RDSQAL_SO
RDSDAT_SI
RDSCLK_SS
INT
SRCCD
SRCMD
GND1
1
2
Test
CODEC
3
4
5
IIC/SPI master
6
Control Inputs
7
8
9
10
SPI display
11
12
13
14 PLL oscillator
15
16
17
18
19
20
RDS
21
22
23
24 SPDIF + Sample Rate Converter
25
75
Debug DSP0 ⁷⁴
73
72
71
Debug DSP1 ₇₀
69
68
67
SAI ⁶⁶
65
64
63
62
61
60
59
58
57
56
55
EMI
54
53
52
51
DBCK0OS01
DSP0 GPIO9
DBIN0OS00
DSP0 GPIO11
DBOUT0
DSP0 GPIO10
DBRQN1
DBCK1_OS11 DSP1 GPIO9
DBIN1_OS10 DSP1 GPIO11
DBOUT1
DSP1 GPIO10
LRCKR
SCKR
LRCKT
SCKT
SDI0
SRCCDC
SDI1 / SRA<21> DSP1 GPIO5
SDI2 / SRA<20> DSP1 GPIO6
SDO0 / SRA<19>
SDO1 / SRA<18> DSP1 GPIO7
SDO2 / SRA<17> DSP1 GPIO8
CASALE
DRD
DWR
SRA<16>
DSP0 GPIO8
SRA<15>
SRA<14>
SRA<13>
CVDD2
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