TDA7500 Datasheet, PDF (4/14 Pages) STMicroelectronics – DIGITAL AM/FM SIGNAL PROCESSOR

TDA7500
PIN DESCRIPTION (continued)
N°
NAME
20 RDSARI_SCK/DSP1_GPIO3
21 RDSQAL_SO/DSP1_GPIO2
22 RDSDAT_SI/DSP1_GPIO1
23 RDSCLK_SS/DSP1_GPIO0
24 INT
25 CGND1
26 CVDD1
27 SCRCCD
28 SCRCMD
29 DSRA<7>
30 DSRA<6>
31 DSRA<5>
32 DSRA<4>
33 DSRA<3>
34 DSRA<2>
35 DSRA<1>
36 DSRA<0>
37 SRA<0>
38 SRA<1>
TYPE
DESCRIPTION
O SPI Bit Clock (Input)/ARI indicator (Output)/General Purpose I/O
(Input/Output). Schmitt trigger input. If SPI interface is enabled,
behaves as SPI bit clock. Optionally it provides the ARI indication
bit. Optionally it can be used as general purpose I/O controlled by
DSP1.
O SPI Slave Output Serial Data (Output)/RDS Bit Quality
(Output)/General Purpose I/O (Input/Output). If SPI is enabled,
behaves as Serial Data Output. Optionally it provides the RDS
serial data quality information. Optionally it can be used as general
purpose I/O controlled by DSP1.
I SPI Slave Input Serial Data (Input)/RDS Bit Data (Output)/General
Purpose I/O (Input/Output). If SPI is enabled, behaves as Serial
Data Input. Optionally it provides the RDS serial data stream.
Optionally it can be used as general purpose I/O controlled by
DSP1.
I SPI Chip Select (Input)/RDS Bit Clock (Output)/General Purpose
I/O (Input/Output). If SPI is enabled, behaves as Chip Select line
for SPI bus. Optionally it provides the 1187.5Hz RDS Bit Clock.
Optionally it can be used as general purpose I/O controlled by
DSP1.
I External interrupt line (Input). When this line is asserted low, the
DSP may be interrupted.
Ground pin dedicated to the digital core part.
Supply pin dedicated to the digital core part.
I SPDIF Input 1 (Input). Stereo SPDIF input to connect a digital
audio source like a CD.
I SPDIF Input 2 (Input). Stereo SPDIF input to connect a digital
audio source like a MD.
I/O DSP SRAM Data Lines<7> (Input/Output). When in SRAM Mode
this pin act as the EMI data line 7.
I/O DSP SRAM Data Lines<6> (Input/Output). When in SRAM Mode
this pin act as the EMI data line 6.
I/O DSP SRAM Data Lines<5> (Input/Output). When in SRAM Mode
this pin act as the EMI data line 5.
I/O DSP SRAM Data Lines<4> (Input/Output). When in SRAM Mode
this pin act as the EMI data line 4.
I/O DSP SRAM Data Line<3> (Input/Output)/DSP DRAM Data
Line<3> (Input/Output). This pin act as the EMI data line 3 in both
SRAM Mode and DRAM Mode.
I/O DSP SRAM Data Line<2> (Input/Output)/DSP DRAM Data
Line<2> (Input/Output). This pin act as the EMI data line 2 in both
SRAM Mode and DRAM Mode.
I/O DSP SRAM Data Line<1> (Input/Output)/DSP DRAM Data
Line<1> (Input/Output). This pin act as the EMI data line 1 in both
SRAM Mode and DRAM Mode.
I/O DSP SRAM Data Line<0> (Input/Output)/DSP DRAM Data
Line<0> (Input/Output). This pin act as the EMI data line 0 in both
SRAM Mode and DRAM Mode.
O DSP SRAM Address Line<0> (Output)/DSP DRAM Address
Line<0> (Output). This pin act as the EMI address line 0 in both
SRAM Mode and DRAM Mode.
O DSP SRAM Address Line<1> (Output)/DSP DRAM Address
Line<1> (Output). This pin act as the EMI address line 1 in both
SRAM Mode and DRAM Mode.
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