EF6805U3 Datasheet, PDF (6/31 Pages) STMicroelectronics – 8-BIT MICROCOMPUTER UNIT

EF6805U3
INPUT/OUTPUT LINES (PA0-PA7, PB0-PB7, PC0-
PC7, PD0-PD7) - These 32 liens are arranged into
four 8-bit ports (A, B, C, and D). Ports A, B, and C
are programmable as either inputs or outputs under
software control of the data direction registers
(DDRs). Port D is for digital input only and bit 6 may
be used for a second interrupt INT2. Refer to In-
put/Output Section and Interrupts Section for addi-
tional information.
MEMORY - The MCU is capable of addressing 4096
bytes of memory and I/O registers with its program
counter. The EF6805U3 MCU has implemented
4090 of these bytes. This consists of : 3776 user
ROM bytes, 192 self-check ROM bytes, 112 user
RAM bytes, 7 port I/O bytes, 2 timer registers, and
a miscellaneous register ; see figure 6 for the Ad-
dress map. The user ROM has been split into two
areas. The main user ROM area is from $080 to
$F37. The last 8 user ROM locations at the bottom
of memory are for the interrupt vectors.
Figure 6 : EF6805U3 MCU Address Map.
The MCU reserves the first-16 memory locations for
I/O features, of which 10 have been implemented.
These locations are used for the ports, the port
DDRs, the timer and the INT2 miscellaneous regis-
ter, and the 112 RAM bytes, 31 bytes are shared
with the stack area. The stack must be used with
care when data shares the stack area.
The shared stack area is used during the processing
of an interrupt or subroutine calls to save the
contents of the CPU state. The register contents are
pushed onto the stack in the order shown in figure
7. Since the stack pointer decrements during
pushes, the low order byte (PCL) of the program
counter is stacked first, then the high order four bits
(PCH) are stacked. This ensures that the program
counter is loaded correctly during pulls from the
stack since the stack pointer increments when it
pulls data from the stack. A subroutine call results
in only the program counter (PCL, PCH) contents
being pushed onto the stack ; the remaining CPU re-
gisters are not pushed.
* Caution : Data direction registers (DDRs) are write only, they read as $FF.
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