EF6805U3 Datasheet, PDF (17/31 Pages) STMicroelectronics – 8-BIT MICROCOMPUTER UNIT

Figure 20 : Typical Port I/O Circuitry.
EF6805U3
Data
Direction
Registe r
Bit
1
1
0
Latched
Output
Data
Bit
0
1
X
Output
State
0
1
High -Z **
Input
to
MCU
0
1
Pin
* DDR is a write-only register and reads as all ”1s”.
** Ports B and C are three-state ports.
Port A has optional internal pull-up devices to provide CMOS data
drive capability. See Electrical Characteristic tables for complete in-
formation.
All input/output lines are TTL compatible as both in-
puts and outputs. Port A lines are CMOS compatible
as outputs (mask option) while port B, C, and D lines
are CMOS compatible as inputs. Port D lines are in-
put only ; thus, there is no corresponding DDR.
When programmed as outputs, port B is capable of
sinking 10 milliamperes and sourcing 1 milliampere
on each pin.
The address map (figure 6) gives the addresses
of data registers and data direction registers.
Figure 21 provides some examples of port
connections.
CAUTION
The corresponding DDRs for ports A, B, and C are
write-only registers (registers at $004, $005, $006).
A read operation on these registers is undefined.
Since BSET and BCLR are read-modify-write in
function, they cannot be used to set or clear a single
DDR bit (all ”unaffected” bits would be set). It is re-
commended that all DDR bits in a port be written u-
sing a single-store instruction.
The latched output data bit (see figure 20) must al-
ways be written. Therefore, any write to a port writes
all of its data bits even though the port DDR is set
to input. This may be used to initialize the data re-
gister and avoid undefined outputs ; however, care
must be exercised when using read-modify-write in-
structions, since the data read corresponds to the
pin level if the DDR is an input (zero) and corre-
sponds to the latched output data when the DDR is
an output (one).
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