EF6805U3 Datasheet, PDF (20/31 Pages) STMicroelectronics – 8-BIT MICROCOMPUTER UNIT

EF6805U3
branch condition is true. Otherwise, control pro-
ceeds to the next instruction. The span of relative
addressing is from - 126 to + 129 from the opcode
address. The programmer need not worry about cal-
culating the correct offset when using the Motorola
assembler since it calculates the proper offset and
checks to see if it is within the span of the branch.
INDEXED, NO OFFSET - In the indexed, no offset
addressing mode, the effective address of the argu-
ment is contained in the 8-bit index register. Thus,
this addressing mode can access the first 256 me-
mory locations. These instructions are only one byte
long. This mode is often used to move a pointer
through a table or to hold the address of a frequently
referenced RAM or I/O location.
INDEXED, 8-BIT OFFSET - In the indexed, 8-bit off-
set addressing mode, the effective address is the
sum of the contents of the unsigned 8-bit index re-
gister and the unsigned byte following the opcode.
This addressing mode is useful in selecting the kth
element in an n element table. With this 2-byte ins-
truction, k would typically be in X with the address
of the beginning of the table in the instruction. As
such, tables may begin anywhere within the first 256
addressable locations and could extend as far as lo-
cation 510 ($1FE is the last location at which the ins-
truction may begin).
INDEXED, 16-BIT OFFSET - In the indexed, 16-bit
offset addressing mode, the effective address is the
sum of the contents of the unsigned 8-bit index re-
gister and the two unsigned bytes following the op-
code. This addressing mode can be used in a man-
ner similar to indexed, 8-bit offset, except that this
3-byte instruction allows tables to be anywhere in
memory. As with direct and extended addressing,
the Motorola assembler determines the shortest
form of indexed addressing.
BIT SET/CLEAR - In the bit set/clear addressing
mode, the bit to be set or cleared is part of the op-
code, and the byte following the opcode specifies
the direct address of the byte in which the specified
bit is to be set or cleared. Thus, any read/write bit in
the first 256 locations of memory, including I/O, can
be selectively set or cleared with a single 2-byte ins-
truction.
Caution
The corresponding DDRs for ports A, B, and C
are write-only registers (registers at $004, $005,
and $006). A read operation on these registers
is undefined. Since BSET and BCLR are read-
modify-write functions, they cannot be used to
set or clear a DDR bit (all ”unaffected” bits would
20/31
be set). It is recommended that all DDR bits in a
port be written using a single-store instruction.
BIT TEST AND BRANCH - The bit test and branch
addressing mode is a combination of direct addres-
sing and relative addressing. The bit and condition
(set or clear) which is to be tested is included in the
opcode, and the address of the byte to be tested is
in the single byte immediately following the opcode
byte. The signed relative 8-bit offset is in the third
byte and is added to the value of the PC if the branch
condition is true. This single 3-byte instruction allows
the program to branch based on the condition of any
readable bit in the first 256 locations of memory. The
span of branching is from - 125 to + 130 from the op-
code address. The state of the tested bit is also
transferred to the carry bit of the condition code re-
gister.
Caution
The corresponding DDRs for ports A, B, and C
are write-only registers (registers at $004, $005,
and $006). A read operation on these registers
is undefined. Since BSET and BCLR are read-
modify-write functions, they cannot be used to
set or clear a DDR bit (all ”unaffected” bits would
be set). It is recommended that all DDR bits in a
port be written using a single-store instruction.
INHERENT - In the inherent addressing mode, all
the information necessary to execute the instruction
is contained in the opcode. Operations specifying
only the index register or accumulator, as well as
control instruction with no other arguments, are in-
cluded in this mode. These instructions are one byte
long.
INSTRUCTION SET
The EF6805U3 MCU has a set of 59 basic instruc-
tions, which when combined with the 10 addressing
modes produce 207 usable opcodes. They can be
divided into five different types : register/memory,
read-modify-write, branch, bit manipulation, and
control. The following paragraphs briefly explain
each type. All the instructions within a given type are
presented in individual tables.
REGISTER/MEMORY INSTRUCTIONS - Most of
these instructions use two operands. One operand
is either the accumulator or the index register. The
other operand is obtained from memory using one
of the addressing modes. The jump unconditional
(JMP) and jump to subroutine (JSR) instructions
have no register operands. Refer to table 1.
READ-MODIFY-WRITE MODIFICATIONS - These
instructions read a memory location or a register,