EF6805U3 Datasheet, PDF (15/31 Pages) STMicroelectronics – 8-BIT MICROCOMPUTER UNIT

Figure 18 : RESET and interrupt Processing Flowchard.
EF6805U3
NOTE
The timer and INT2 interrupts share the same vector
address. The interrupt routine must determine the
source by examining the interrupt request bits (TCR
b7 and MR b7). Both TCR b7 and MR b7 can only
be written to zero by software.
The external interrupt, INT and INT2, are synchro-
nized and then latched on the falling edge of the in-
put signal. The INT2 interrupt has an interrupt re-
quest bit (bit 7) and a mask bit (bit 6) located in the
miscellaneous register (MR). The INT2 interrupt is
inhibited when the mask bit is set. The INT2 is al-
ways read as a digital input on port D. The INT2 and
timer interrup requests bits, if set, cause the MCU to
process an interrupt when the condition code I bit is
clear.
A sinuoidal input signal (f_INT maximum) can be used
to generate an external interrupt for use as a zero-
crossing detector. This allows applications such as
servicing time-of-day routines and engaging/disen-
gaging ac power control devices. Off-chip full wave
rectification provides an interrupt at every zero cros-
sing of the ac signal and thereby provides a 2f clock.
See figure 19.
NOTE
The INT (pin 3) is internally biased at approximately
2.2V due to the internal zero-crossing detection.
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