ST10F272 Datasheet, PDF (57/179 Pages) STMicroelectronics – 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM

ST10F272
Table 29. X-Interrupt detailed mapping (continued)
XP0INT
XP1INT
ASC1 Error
PLL Unlock / OWD
PWM1 Channel 3...0
Interrupt system
XP2INT
x
XP3INT
x
x
x
9.2
Note:
Exception and error traps list
Table 30 shows all of the possible exceptions or error conditions that can arise during run-
time.
Table 30. Trap priorities
Exception Condition
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps:
Undefined Opcode
MAC Interruption
Protected Instruction Fault
Illegal word Operand Access
Illegal Instruction Access
Illegal External Bus Access
Reserved
Software Traps
TRAP Instruction
RESET
RESET
RESET
00’0000h
00’0000h
00’0000h
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008h
00’0010h
00’0018h
UNDOPC
MACTRP
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
[002Ch - 003Ch]
Any
0000h – 01FCh
in steps of 4h
00h
00h
00h
02h
04h
06h
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
[0Bh - 0Fh]
Any
[00h - 7Fh]
Trap*
Priority
III
III
III
II
II
II
I
I
I
I
I
I
Current
CPU
Priority
* - All the class B traps have the same trap number (and vector) and the same lower priority
compare to the class A traps and to the resets.
- Each class A traps has a dedicated trap number (and vector). They are prioritized in the
second priority level.
- The resets have the highest priority level and the same trap number.
- The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are
serviced.
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