ST10F272 Datasheet, PDF (174/179 Pages) STMicroelectronics – 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM

Electrical characteristics
Figure 61. SSC master timing
SCLK
MTSR
MRST
1)
t₃₀₀
t₃₀₁ t₃₀₂
2)
t₃₀₄
t₃₀₃
t₃₀₅
t₃₀₅
t₃₀₆
1st out bit 2nd out bit
t₃₀₇ t₃₀₈
1st in bit
2nd In bit
ST10F272
t₃₀₅
Last out bit
t₃₀₇ t₃₀₈
Last in bit
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
24.8.20.2 Slave mode
V_DD = 5V ±10%, V_SS = 0V, T_A = -40 to +125°C, C_L = 50pF
Table 82. SSC slave mode timings
Symbol
Parameter
Max. Baudrate
6.6 MBd ⁽¹⁾⁾
@F_CPU = 40MHz
(<SSCBR> = 0002h)
Variable Baudrate
(<SSCBR> = 0001h -
FFFFh)
Unit
min.
t₃₁₀
SR SSC clock cycle time⁽²⁾
150
t₃₁₁
SR SSC clock high time
63
t₃₁₂
SR SSC clock low time
63
t₃₁₃
SR SSC clock rise time
–
t₃₁₄
SR SSC clock fall time
–
t₃₁₅
CC Write data valid after shift edge
–
t₃₁₆
CC Write data hold after shift edge
0
Read data setup time before latch
t_317p
SR edge, phase error detection on
62
(SSCPEN = 1)
Read data hold time after latch
t_318p
SR edge, phase error detection on
87
(SSCPEN = 1)
max.
150
–
–
10
10
55
–
–
min.
max.
8TCL
262144 TCL ns
t₃₁₀ / 2 – 12
–
ns
t₃₁₀ / 2 – 12
–
ns
–
10
ns
–
10
ns
–
2TCL + 30 ns
0
–
ns
4TCL + 12
–
ns
–
6TCL + 12
–
ns
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