ST10F272 Datasheet, PDF (108/179 Pages) STMicroelectronics – 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM

Power reduction modes
ST10F272
21.3.1
In normal running mode (that is when main V_DD is on) the V_STBY pin can be tied to V_SS
during reset to exercise the EA functionality associated with the same pin: the voltage
supply for the circuitries which are usually biased with V_STBY (see in particular the 32 kHz
oscillator used in conjunction with Real Time Clock module), is granted by the active main
V_DD.
It must be noted that Stand-by Mode can generate problems associated with the usage of
different power supplies in CMOS systems; particular attention must be paid when the
ST10F272 I/O lines are interfaced with other external CMOS integrated circuits: if V_DD of
ST10F272 becomes (for example in Stand-by Mode) lower than the output level forced by
the I/O lines of these external integrated circuits, the ST10F272 could be directly powered
through the inherent diode existing on ST10F272 output driver circuitry. The same is valid
for ST10F272 interfaced to active/inactive communication buses during Stand-by mode:
current injection can be generated through the inherent diode.
Furthermore, the sequence of turning on/off of the different voltage could be critical for the
system (not only for the ST10F272 device). The device Stand-by mode current (I_STBY) may
vary while V_DD to V_STBY (and vice versa) transition occurs: some current flows between V_DD
and V_STBY pins. System noise on both V_DD and V_STBY can contribute to increase this
phenomenon.
Entering stand-by mode
As already said, to enter Stand-by Mode XRAM2EN bit in the XPERCON Register must be
cleared: this allows to freeze immediately the RAM interface, avoiding any data corruption.
As a consequence of a RESET event, the RAM Power Supply is switched to the internal
low-voltage supply V_18SB (derived from V_STBY through the low-power voltage regulator).
The RAM interface will remain frozen until the bit XRAM2EN is set again by software
initialization routine (at next exit from main V_DD power-on reset sequence).
Since V₁₈ is falling down (as a consequence of V_DD turning off), it can happen that the
XRAM2EN bit is no longer able to guarantee its content (logic “0”), being the XPERCON
Register powered by internal V₁₈. This does not generate any problem, because the Stand-
by Mode switching dedicated circuit continues to confirm the RAM interface freezing,
irrespective the XRAM2EN bit content; XRAM2EN bit status is considered again when
internal V₁₈ comes back over internal stand-by reference V_18SB.
If internal V₁₈ becomes lower than internal stand-by reference (V_18SB) of about 0.3 to 0.45V
with bit XRAM2EN set, the RAM Supply switching circuit is not active: in case of a
temporary drop on internal V₁₈ voltage versus internal V_18SB during normal code execution,
no spurious Stand-by Mode switching can occur (the RAM is not frozen and can still be
accessed).
The ST10F272 Core module, generating the RAM control signals, is powered by internal
V₁₈ supply; during turning off transient these control signals follow the V₁₈, while RAM is
switched to V_18SB internal reference. It could happen that a high level of RAM write strobe
from ST10F272 Core (active low signal) is low enough to be recognized as a logic “0” by the
RAM interface (due to V₁₈ lower than V_18SB): The bus status could contain a valid address
for the RAM and an unwanted data corruption could occur. For this reason, an extra
interface, powered by the switched supply, is used to prevent the RAM from this kind of
potential corruption mechanism.
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