WARP11 Datasheet, PDF (5/19 Pages) STMicroelectronics – WEIGHT ASSOCIATIVE RULE PROCESSOR

W.A.R.P.1.1
add7 add6 add5 add4 add3 add2 add1 add0
cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0
cs2 cs1 cs0 add6 add5 add4 add3 add2 add1 add0
A9
A0
This resulting word allows to identify the appropri-
ate memory [cs2-cs0] and its respective address
[add6-add0] where the relative I0-I7 are to be
stored.
When the CHM pin is high, during the off-line
phase, W.A.R.P. generates the addresses for its
internal memories and send those addresses to the
single external memory support where data (.dat
file) are located. These addresses, which are sent
by means of the EPA0-EPA2 and A0-A9 (EPA0
MSB, A9 LSB) output pins, allow to identify the
data (on the EPROM) that have be loaded in
W.A.R.P. internal memories.
In on-line mode A0-A9 are not used.
I0-I7: During the off-line phase these 8 data input
pins accept the microcode configuration and data
to be written into the internal memories. The ante-
cedent memory word size is 64 bits, so it is neces-
sary to give each word 8 bits at a time. In the same
way are written the words of consequent memory
and of program memory.
In on-line mode this bus carries the input variables
to W.A.R.P.. Input values have a resolution of 6 or
7 bits in accordance with the configuration setting.
PRST: This is the restart pin of W.A.R.P.. It is
possible to restart the work during the computation
(on-line phase) or before the writing of internal
memories (off-line phase). In both cases it must be
put low at least for a clock period.
FIN: During the on-line phase it will start the run-
time acquisition cycle. This pin is activated by
providing a positive pulse for a time no lower than
an entire clock period. When all expected inputs
have been processed, a new FIN pulse must be
sent to activate a new process.
OFL: When this pin is high, the chip is enabled to
load data in the internal RAMs (off-line phase). It
must be low when the fuzzy controller is waiting for
input values and during the processing phase (on-
line phase).
CHM:This pin, which is used only during the off-line
phase, determines the charge mode. CHM is not
present in W.A.R.P. 1.0 release.
When CHM is low the addresses of the internal
memory locations where data have to be stored
must be sent to W.A.R.P. from the outside by
means of the input pins A0-A9.
When CHM is high W.A.R.P. automatically gener-
ates the addresses of its internal memories and
manages the EPROMs reading by means of the
addresses contained in EPA0-EPA2 and A0-A9
output pins (13 bits).
TE: For testing purpose only. It must be connected
to V_SS.
MTE: For testing purpose only. It must be con-
nected to VSS.
MCLK: This is the input master clock whose fre-
quency can reach up to 40MHz (MAX).
During the off-line phase with CHM high, the
DCLK signal with a frequency of MCLK/32 is gen-
erated in order to drive the downloading phase
timing.
EPA0-EPA2: During the off-line phase and in cor-
respondencewith CHM high, these output pins are
joined (as MSB) to A0-A9 to obtaine the complete
address of the memory support where to read the
data to be loaded in W.A.R.P. internal memories.
EPA0-EPA2 are not used when CHM is low or in
W.A.R.P. 1.0 release.
O0-O9: These pins carry out the output values.
When the STB (strobe pin) is high, one output
variable can be read by external devices (in on-line
mode). The resolution of output variables is 1024
points (10 bits). If there are more than one output,
the output variables are calculated one by one and
they are provided in the sequence stabilized during
the editing phase (see W.A.R.P.-SDT User Man-
ual).
OCNT0-OCNT3: This 4 bit output bus provides the
output variables with a progressive number during
the on-line phase. As a consequenceit is possible
to know to which variable correspond the data that
are on the output data bus (O0-O9). The dimension
of OCNT bus is connected with the maximum
number of output variables (16).
STB: The strobe pin enables the user to utilize the
output. When this pin is high it indicates that a new
output variable has been calculated and it is ready
on the output bus (O0-O9). This signal synchro-
nizes the external devices and in particular the
interfaces with the controlled processes (on-line
mode).
EP: This signal low indicates that the processing
of all the rules has been completed.
NP: This output pin indicates that a new process
can start. NP is automatically set low before the
last output has been calculated, so that it is possible
to start a new data acquisition before (with a new
FIN) the computation is terminated.
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