WARP11 Datasheet, PDF (11/19 Pages) STMicroelectronics – WEIGHT ASSOCIATIVE RULE PROCESSOR

W.A.R.P.1.1
W.A.R.P. TIMING TABLES
Off-line Phase Timing (Internal RAMs Loading with Charge Mode ”0”)
OFL
F IN d e te c tio n
D ATA 0 a c q u is iti o n
D ATA 1 a c q u is iti o n
D ATA n a c q u is it io n
MC LK
F IN
I0 -I6
D ATA 0
T_{A C Q}
D ATA 1
D ATA n
NP
EP
T_{A C Q = 2 0 0 n s fo r a c o n fig u r a tio n w ith 1 6 in p u t s , 8 o u tp u t s , 2 8 r u le s}
Timing Table Description: OFF-LINE phase (CHM ”0”)
- CHM [INPUT] low will enable the ’manual downloading’ by specifying the address and data to be loaded
into W.A.R.P..
- MCLK [INPUT] must be connected with the external synchronization signal.
- PRST [INPUT] must be set high to enable the device.
- OFL [INPUT] must be set high to enable the configurationloading phase into the internal RAMs of W.A.R.P..
- The input to be written into the internal memories at the address specified in A0-A9 must be put into I0-I7
bus .
- SYNC [OUTPUT] will be provided to synchronize input data (I0-I7,A0-A9) coming from an external
database. SYNC frequency is MCLK/32 with a phase delay of tCSP ns . W.A.R.P. stores the data present
on input buses at the rising edge of MCLK, returns a SYNC pulse after t_CSP ns indicating that is waiting for
new data and address that must be given within next 31MCLK pulses. Afterwards W.A.R.P. stores the data
on input buses and restores a new SYNC pulse.
W.A.R.P. stores the data situated in I0-I7 and the addresses A0-A9 into its internal registers.
Figure 8. Block Diagram for W.A.R.P. downloading (CHM ”0”)
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