WARP11 Datasheet, PDF (4/19 Pages) STMicroelectronics – WEIGHT ASSOCIATIVE RULE PROCESSOR

W.A.R.P.1.1
Table 4. Pin Description
Name
VDD
VSS
A0-A9
I0-I7
PRST
FIN
OFL
CHM
TE
MTE
MCLK
EPA0-EPA2^*
O0-O9
OCNT0-OCNT3
STB
EP
NP
OTST
OMTS
SYNC
Pins Type
-
-
I/O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
* _{Pins not used in W.A.R.P. 1.0}
Functions in dedicated memories in order to reduce
the computational time. Therefore a great amount
of W.A.R.P. processing is based on a look-up table
approach rather than on on-line calculation.
Those Membership Functions (MFs), each one
portrayed by a configurable resolution of 2⁶ or 2⁷
elements, are stored in four internal RAMs (1Kbyte
each). The consequent MFs, due to the different
modelling, are loaded in a single RAM by storing
for each MF its area and its barycentre. This is due
to the adoption of the Center of Gravity defuzzifica-
tion method.
The downloading phase allows the setting of the
device, in terms of I/O number, universes of dis-
course and MF shapes. During this phase W.A.R.P.
prepares its internal memories for the on-line
elaboration phase and loads the microcode in its
program memory. This microcode, which drives the
on-line phase, is generated by the Compiler (see
W.A.R.P.-SDT User Manual) according to the
adopted configuration. The possible configurations
are shown in table 1.
During the on-line phase (up to 40MHz working
frequency), W.A.R.P. processes the input data and
produces its outputs according to the configuration
loaded in the downloading phase.
W.A.R.P. is conceived to work together with tradi-
Function
Power Supply
Ground
Memory Address Bus
Data Input Bus
Preset
First Input Signal
Off-Line/On-Line Switch
Charge Mode Switch
Testing (it must be connected to V_SS)
Testing (it must be connected to VSS)
Clock (up to 40 MHz)
EPROM Address Bus
Defuzzified Output
Output Counter
Strobe (Output Ready Signal)
End Process
New Process
Testing (it must be connected to VSS)
Testing (it must be connected to V_SS)
External Synchronization
tional microcontrollers which shall perform normal
control tasks while W.A.R.P. will be indipendently
responsible for all the fuzzy related computing.
W.A.R.P. is manufactured using the high perform-
ance, reliable HCMOS4T (O.7µm) SGS-THOM-
SON Microelectronics process.
PIN DESCRIPTION
V_DD, V_SS: Power is supplied to W.A.R.P. using
these pins. V_DD is the power connection and V_SS is
the ground connection; multi-connections are nec-
essary.
A0-A9: When the CHM pin is low they accept as
input the addresses for the internal memory bus. In
the off-line mode they are used to address W.A.R.P.
memories where the microprogram and data of
antecedent and consequentmembership functions
must be loaded.
Each A0-A9 word is composed by assembling the
data contained in the memory support related to .cs
and .add files (see W.A.R.P.-SDT User Manual). In
particular, couples of data respectively coming from
.cs and .add files are joined to form a single A0-A9
word in the following way:
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