STD3N40K3 Datasheet, PDF (5/16 Pages) STMicroelectronics – Gate charge minimized

STD3N40K3
Electrical characteristics
Table 6. Switching times
Symbol
Parameter
t_d(on)
t_r
t_d(off)
t_f
Turn on delay time
Rise time
Turn off delay time
Fall time
Test conditions
V_DD = 200 V, I_D = 0.6,
R_G = 4.7 Ω, V_GS = 10 V
(see Figure 15)
Min.
-
Typ.
7
8
18
14
Max. Unit
ns
ns
-
ns
ns
Table 7. Source drain diode
Symbol
Parameter
Test conditions
I_SD
I_SDM ⁽¹⁾
Source-drain current
Source-drain current
(pulsed)
V_SD ⁽²⁾ Forward on voltage
I_SD = 1.8 A, V_GS = 0
t_rr
Q_rr
I_RRM
Reverse recovery time I_SD = 1.8 A, di/dt = 100 A/µs
Reverse recovery charge V_DD = 60 V
Reverse recovery current (see Figure 17)
t_rr
Q_rr
I_RRM
Reverse recovery time I_SD = 1.8 A, di/dt = 100 A/µs
Reverse recovery charge V_DD = 60 V, T_j = 150 °C
Reverse recovery current (see Figure 17)
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Min.
-
-
-
-
Typ.
145
490
7
166
580
7
Max. Unit
1.8 A
7.2 A
1.5 V
ns
nC
A
ns
nC
A
Table 8. Gate-source Zener diode
Symbol
Parameter
Test conditions
BV_GSO
Gate-source breakdown
voltage
Igs=± 1 mA (open drain)
Min. Typ. Max. Unit
30
-
V
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
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