STD3LN80K5 Datasheet, PDF (5/15 Pages) STMicroelectronics – Ultra-low gate charge

STD3LN80K5
Symbol
Parameter
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 7: Switching times
Electrical characteristics
Test conditions
Min. Typ. Max. Unit
VDD = 400 V, ID = 1 A, RG = 4.7 Ω,
- 6.2
-
ns
VGS = 10 V ( see Figure 14: "Test
circuit for resistive load switching
times" and Figure 19: "Switching
-
7
-
ns
-
30
-
ns
time waveform" )
-
26
-
ns
Symbol
Parameter
Table 8: Source drain diode
Test conditions
Min. Typ. Max. Unit
ISD
ISDM⁽¹⁾
VSD⁽²⁾
trr
Qrr
IRRM
Source-drain current
Source-drain current
(pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery
charge
Reverse recovery
current
-
-
ISD = 2 A, VGS = 0 V
-
ISD = 2 A, di/dt = 100 A/µs,
-
VDD = 60 V ( see Figure 16: "Test
circuit for inductive load
-
switching and diode recovery
times" )
-
2
A
8
A
1.5 V
210
ns
0.8
µC
7.6
A
trr
Reverse recovery time
ISD = 2 A, di/dt = 100 A/µs,
- 345
ns
Qrr
Reverse recovery
charge
VDD = 60 V, Tj = 150 °C, (see
Figure 16: "Test circuit for
- 1.2
µC
IRRM
Reverse recovery
current
inductive load switching and
diode recovery times" )
- 7.2
A
Notes:
(1)_{Pulse width limited by safe operating area.}
(2)_{Pulsed: pulse duration = 300 µs, duty cycle 1.5%.}
Symbol
V(BR)GSO
Table 9: Gate-source Zener diode
Parameter
Test conditions
Gate-source breakdown voltage IGS = ± 1 mA, ID = 0 A
Min. Typ. Max. Unit
30
-
-
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD
performance of the device. The Zener voltage facilitates efficient and cost-effective device
integrity protection, thus eliminating the need for additional external componentry.
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