STD3LN80K5 Datasheet, PDF (4/15 Pages) STMicroelectronics – Ultra-low gate charge

Electrical characteristics
STD3LN80K5
2
Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 5: On /off states
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown
voltage
ID = 1 mA, VGS = 0 V
Zero gate voltage
IDSS
drain current
Gate body leakage
IGSS
current
VDS = 800 V, VGS = 0 V
VDS = 800 V, VGS = 0 V,
TC = 125 °C⁽¹⁾
VGS = ± 20 V, VGS = 0 V
VGS(th)
RDS(on)
Gate threshold voltage
Static drain-source
on-resistance
VDS = VGS, ID = 100 µA
VGS = 10 V, ID = 1 A
Min. Typ. Max. Unit
800
V
1 µA
50 µA
±10 µA
3
4
5
V
2.75 3.25 Ω
Notes:
(1)_{Defined by design, not subject to production test.}
Symbol
Ciss
Coss
Crss
Cotr⁽¹⁾
Coer⁽²⁾
RG
Qg
Qgs
Qgd
Table 6: Dynamic
Parameter
Test conditions
Input capacitance
Output capacitance
Reverse transfer capacitance
VDS = 100 V, f = 1 MHz,
VGS = 0 V
Equivalent capacitance time
related
Equivalent capacitance
energy related
VDS = 0 to 640 V, VGS = 0 V
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
f = 1 MHz, ID = 0 A
VDD = 640 V, ID = 2 A,
VGS = 10 V ( see Figure 15:
"Test circuit for gate charge
behavior" )
Min. Typ.
- 102
- 11
- 0.1
- 20
-
7
- 12
- 2.63
- 0.91
- 1.53
Max.
-
-
-
-
-
-
-
-
-
Unit
pF
pF
pF
pF
pF
Ω
nC
nC
nC
Notes:
(1)_{Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS}
increases from 0 to 80% VDSS
(2)_{Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS}
increases from 0 to 80% VDSS
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