ST72325XXX Datasheet, PDF (47/243 Pages) STMicroelectronics – SCI asynchronous serial interface

ST72325xxx-Auto
Supply, reset and clock management
Figure 14. RESET sequences
V_DD
V_IT+(LVD)
V_IT-(LVD)
RUN
LVD
RESET
Active Phase
RUN
SHORT EXT.
RESET
Active
Phase
RUN
LONG EXT.
RESET
Active
Phase
RUN
WATCHDOG
RESET
Active
Phase
RUN
t_w(RSTL)out
t_w(RSTL)out
t_h(RSTL)in
t_h(RSTL)in
t_w(RSTL)out
DELAY
EXTERNAL
RESET
) ^SOURCE
t(s _{RESET PIN}
duc WATCHDOG
lete ^{Pro RESET}
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 T_CPU)
VECTOR FETCH
Obso _6.6
Obsolete ^{Product(s) - 6.6.1}
System integrity management (SI)
The System Integrity Management block contains the Low Voltage Detector (LVD) and
Auxiliary Voltage Detector (AVD) functions and Clock Security System (CSS). It is managed
by the SICSR register.
Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the V_DD supply
voltage is below a V_IT- reference value. This means that it secures the power-up as well as
the power-down keeping the ST7 in reset.
The V_IT- reference value for a voltage drop is lower than the V_IT+ reference value for power-
on in order to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).
The LVD reset circuitry generates a reset when V_DD is below:
– V_IT+ when V_DD is rising
– V_IT- when V_DD is falling
The LVD function is illustrated in Figure 15.
The voltage threshold can be configured by option byte to be low, medium or high.
Doc ID 13770 Rev 3
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