ST72325XXX Datasheet, PDF (117/243 Pages) STMicroelectronics – SCI asynchronous serial interface

ST72325xxx-Auto
Table 59. Timer modes
Modes
Input
Capture 1
Timer resources
Input
Capture 2
Output
Compare 1
One Pulse mode
Not
recommended⁽¹⁾
No
No
PWM mode
Not
recommended⁽³⁾
1. See Note 4 in Section 13.3.6 One Pulse mode
2. See Note 5 in Section 13.3.6 One Pulse mode
3. See Note 4 in Section 13.3.7 Pulse width modulation mode
16-bit timer
Output
Compare 2
Partially⁽²⁾
No
13.7 16-bit timer registers
uct(s) _13.7.1
Each timer is associated with 3 control and status registers, and with 6 pairs of data
registers (16-bit values) relating to the 2 input captures, the 2 output compares, the counter
and the alternate counter.
Control register 1 (CR1)
rod _CR1
te ^{P 7}
le ^ICIE
so RW
6
OCIE
RW
5
TOIE
RW
4
FOLV2
RW
3
FOLV1
RW
Reset value: 0000 0000 (00h)
2
1
0
OLVL2
IEDG1
OLVL1
RW
RW
RW
Ob _{Table 60. CR1 register description}
) ^{- Bit Name}
Function
t(s ^{Input Capture Interrupt Enable}
duc ^{7 ICIE}
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is
set.
ro_{Output Compare Interrupt Enable}
lete ^{P 6 OCIE}
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register
is set.
o _{Timer Overflow Interrupt Enable}
bs ^{5 TOIE} 0: Interrupt is inhibited
O ^{1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.}
Forced Output Compare 2
4 FOLV2
This bit is set and cleared by software.
0: No effect on the OCMP2 pin
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and
even if there is no successful comparison
Doc ID 13770 Rev 3
117/243