ST72325XXX Datasheet, PDF (133/243 Pages) STMicroelectronics – SCI asynchronous serial interface

ST72325xxx-Auto
Serial peripheral interface (SPI)
Figure 62. Clearing the WCOL bit (Write Collision Flag) software sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
2nd Step
Read SPIDR
RESULT
SPIF = 0
WCOL = 0
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
2nd Step
Read SPICSR
Read SPIDR
RESULT
WCOL = 0
Note: Writing to the SPIDR register
instead of reading it does not reset the
WCOL bit.
14.5.4 Single master systems
Obsolete ^{Product(s) - Obsolete Product(s) Note:}
A typical single master system may be configured, using an MCU as the master and four
MCUs as slaves (see Figure 63).
The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to be
inputs at that time, thus disabling the slave devices.
To prevent a bus conflict on the MISO line the master allows only one active slave device
during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master will receive the previous byte back from the slave device if all MISO and
MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
Figure 63. Single master / multiple slave configuration
SS
SCK
Slave
MCU
MOSI MISO
SS
SCK
Slave
MCU
MOSI MISO
SS
SCK
Slave
MCU
MOSI MISO
SS
SCK
Slave
MCU
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
Doc ID 13770 Rev 3
133/243