ST72325XXX Datasheet, PDF (154/243 Pages) STMicroelectronics – SCI asynchronous serial interface

Serial communications interface (SCI)
ST72325xxx-Auto
15.7.3
Table 75. SCICR1 register description (continued)
Bit Name
Function
Parity interrupt enable
0 PIE
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
Control register 2 (SCICR2)
SCICR2
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
RW
RW
RW
RW
RW
RW
RW
RW
) Table 76. SCICR2 register description
t(s ^{Bit Name}
Function
uc Transmitter interrupt enable
Prod ^{7 TIE}
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.
te ^{Transmission complete interrupt enable}
sole ^{6 TCIE}
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.
b _{Receiver interrupt enable}
t(s) ^{- O 5 RIE}
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR
register.
c _{Idle line interrupt enable}
rodu ^{4 ILIE}
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.
te ^{P Transmitter enable}
This bit enables the transmitter. It is set and cleared by software.
le _{0: Transmitter is disabled}
o _{1: Transmitter is enabled}
Obs ^{3 TE}
Notes:
During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble
(idle line) after the current word.
When TE is set there is a 1 bit-time delay before the transmission starts.
Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits
are both cleared (or if TE is never set).
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