STDVE103A Datasheet, PDF (38/43 Pages) STMicroelectronics – Adaptive 3.4 Gbps 3:1 TMDS/HDMI signal equalizer

Application information
6
Application information
STDVE103A
6.1
Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is recommended to
always apply V_CC before applying any signals to the input/output or control pins.
6.2
Power supply requirements
Bypass each of the V_CC pins with 0.1 μF and 1 nF capacitors in parallel as close to the
device as possible, with the smaller-valued capacitor as close to the V_CC pin of the device as
possible.
All V_CC pins can be tied to a single 3.3 V power source. A 0.01 μF capacitor is connected
from each V_CC pin directly to ground to filter supply noise. The maximum power supply
variation can only be ±5% as per the HDMI specifications.
The maximum tolerable noise ripple on 3.3 V supply must be within a specified limit.
6.3
Differential traces
The high-speed TMDS inputs are the most critical parts for the device. There are several
considera-tions to minimize discontinuities on these transmission lines between the
connectors and the device.
(a) Maintain 100-Ω differential transmission line impedance into and out of the STDVE103A.
(b) Keep an uninterrupted ground plane below the high-speed I/Os.
(c) Keep the ground-path vias to the device as close as possible to allow the shortest return
current path.
(d) Layout of the TMDS differential inputs should be with the shortest stubs from the
connectors.
Output trace characteristics affect the performance of the STDVE103A. Use controlled
impedance traces to match trace impedance to both the transmission medium impedance
and termination resistor. Run the differential traces close together to minimize the effects of
the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities
in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to
further prevent impedance discontinuities.
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