STDVE103A Datasheet, PDF (12/43 Pages) STMicroelectronics – Adaptive 3.4 Gbps 3:1 TMDS/HDMI signal equalizer

Functional description
4
Functional description
STDVE103A
The STDVE103A routes physical layer signals for high bandwidth digital video and is
compatible with low voltage differential signaling standards such as the TMDS. The device
passes the differential inputs from a video source to a common display when it is in the
active mode of operation. The device conforms to the TMDS standard on both inputs and
outputs.
The low on-resistance and low I/O capacitance of the switch in STDVE103A result in a very
small propagation delay. The device integrates SPDT-type switches for 3 differential data
TMDS channels and 1 differential clock channel. Additionally, it integrates the switches for
DDC and HPD line switching with I²C repeater on the DDC lines.
The I²C interface of the selected input port is linked to the I²C interface of the output port,
and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the
unused ports, the I²C interfaces are isolated and the HPD pins are driven to L state.
4.1
Adaptive equalizer
The equalizer dramatically reduces the intersymbol interference (ISI) jitter and attenuation
from long or lossy transmission media. The inputs present high impedance when the device
is not active or when V_CC is absent or 0 V. In all other cases, the 50 Ω termination resistors
on input channels are present.
This circuit helps to improve the signal eye pattern significantly. Shaping is performed by the
gain stage of the equalizer to compensate the signal degradation and then the signals are
driven on to the output ports.
The equalizer is fully adaptive and automatic in function providing smaller gain at low
frequencies and higher gain at high frequencies. The equalizer is optimized internally for an
adaptive operation.
Table 3.
Gain frequency response
Frequency
(MHz)
225
325
410
825
1650
Gain in dB
3
5
6.5
11
16
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