RHF1401_12 Datasheet, PDF (35/42 Pages) STMicroelectronics – Rad-hard 14-bit 30 Msps A/D converter

RHF1401
User manual
3.5.3
Digital output load considerations
The features of the internal output buffers limit the maximum load on the digital data output.
In particular, the shape and amplitude of the Data Ready signal, toggling at the clock
frequency, can be weakened by a higher equivalent load.
In applications that impose higher load conditions, it is recommended to use the falling edge
of the master clock instead of the Data Ready signal. This is possible because the output
transitions are internally synchronized with the falling edge of the clock.
Figure 62. Output buffer fall time
25
VCCBE=2.5V
20
VCCBE=3.3V
15
Figure 63. Output buffer rise time
25
VCCBE=2.5V
20
VCCBE=3.3V
15
10
10
5
5
0
0
0
10
20
30
40
50
0
10
20
30
40
50
load capacitor (pF)
load capacitor (pF)
3.6
PCB layout precautions
● The use of dedicated analog and digital ground planes on the PCB is recommended for
high-speed circuit applications to provide low parasitic inductance and resistance.
AGND is connected to the analog ground plane and DGND, GNDBI, GNDBE are
connected to the digital ground plane.
● To minimize the transition current when the output changes, the capacitive load at the
digital outputs must be reduced as much as possible by using the shortest-possible
routing tracks. One way to reduce the capacitive load is to remove the ground plane
under the output digital pins and layers at high sampling frequencies.
● The separation of the analog signal from the clock signal and digital outputs is
mandatory to prevent noise from coupling onto the input signal.
● Power supply bypass capacitors must be placed as close as possible to the IC pins to
improve high-frequency bypassing and reduce harmonic distortion.
● All leads must be as short as possible, especially for the analog input, so as to
decrease parasitic capacitance and inductance.
● Choose the smallest-possible component sizes (SMD).
Doc ID 13317 Rev 8
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