RHF1401_12 Datasheet, PDF (13/42 Pages) STMicroelectronics – Rad-hard 14-bit 30 Msps A/D converter

RHF1401
Electrical characteristics
2.2
Timing characteristics
Table 5. Timing characteristics
Symbol
Parameter
Test conditions
DC Clock duty cycle
F_s = 20 Msps
T_od
Data output delay (fall of
clock to data valid) ⁽¹⁾
10 pF load capacitance
T_pd
Data pipeline delay⁽²⁾
Duty cycle = 50%
T_on
Falling edge of OEB to
digital output valid data
T_off
Rising edge of OEB to
digital output tri-state
T_rD Data rising time
T_fD Data falling time
10 pF load capacitance
10 pF load capacitance
1. As per Figure 11.
2. If the duty cycle does not equal 50%: T_pd = 7 cycles + CLK pulse width.
Figure 11. Timing diagram
Min Typ Max Unit
45 50 65 %
5 7.5 13 ns
7.5 7.5 7.5 cycles
1
ns
1
ns
6
ns
3
ns
N+5
N+4
N+6
N+7
N+8
N- 2
N+3
Analog
input
N-1
N+2
N N+1
CLK
OEB
Data
output
DR
Tod
Tod
Tpd +Tod
Toff
N -8 N -7 N -6 N-5 N -4 N -3
Ton
N-1 N N+1
HZ state
OR
AM06120
The input signal is sampled on the rising edge of the clock while the digital outputs are
synchronized on the falling edge of the clock. The duty cycles on DR and CLK are the same.
The rising and falling edges of the OR pin are synchronized with the falling edge of the DR
pin.
Doc ID 13317 Rev 8
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