RHF1401_12 Datasheet, PDF (33/42 Pages) STMicroelectronics – Rad-hard 14-bit 30 Msps A/D converter

RHF1401
User manual
3.4
Clock input
The quality of the converter very much depends on the accuracy of the clock input in terms
of jitter. The use of a low-jitter, crystal-controlled oscillator is recommended.
The following points should also be considered.
● The clock’s power supplies must be independent of the ADC’s output supplies to avoid
digital noise modulation at the output.
● When powered-on, the circuit needs several clock periods to reach its normal operating
conditions.
Figure 61. Clock input schematic
Square clock
DVcc/2
Sine clock
DVcc/2
CLK
Short track
50 Ω clock generator
50 Ω
CLK
Short track
50 Ω
AM04577
The signal applied to the CLK pin is critical to obtain full performance from the RHF1401.
Below 10 MHz, the sine clock does not have transition times fast enough to achieve good
performances. It is recommended to use a square signal with fast transition times and to
place proper termination resistors as close as possible to the device.
The sampling instant is determined by the clock signal’s rising edge. The jitter associated
with this instant must be as low as possible to avoid SNR degradation on fast moving input
signals. To make sure any error is less than 0.5 LSB, the total jitter T_j must satisfy the
following condition for a full-scale input signal.
T_j < -_π----_â‹------_F----_i-_n--¹--_â‹------₂----_n---₊----₁-
For example, the total jitter with a 14-bit resolution for a 10 MHz full-scale input should be no
more than 1 picosecond (rms).
In most cases, the clock signal jitter is responsible for noise. Therefore, you must pay
attention to the clock signal when fast signals are acquired with a low frequency clock.
Doc ID 13317 Rev 8
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