RHF1401_12 Datasheet, PDF (34/42 Pages) STMicroelectronics – Rad-hard 14-bit 30 Msps A/D converter

User manual
RHF1401
3.5
3.5.1
3.5.2
Operating modes
Extra functionalities are provided to simplify the application board as much as possible. The
operating modes offered by the RHF1401 are described in Table 14.
Table 14. RHF1401 operating modes
Inputs
Outputs
Analog input differential
amplitude
DFSB OEB OR DR
Most significant bit (MSB)
H
(V_IN-V_INB) above maximum range
L
H
(V_IN-V_INB) below minimum range
L
H
(V_IN-V_INB) within range
L
X
X
L H CLK D13
L H CLK D13 complemented
L H CLK D13
L H CLK D13 complemented
L L CLK D13
L L CLK D13 complemented
H
HZ⁽¹⁾
HZ
HZ (all digital outputs are in high
impedance)
1. High impedance.
Digital inputs
Data format select bit (DFSB): when set to low level (V_IL), the digital input DFSB provides
a two’s complement digital output MSB. This can be of interest when performing some
further signal processing. When set to high level (V_IH), DFSB provides standard binary
output coding (see Table 12).
Output enable bit (OEB): when set to low level (V_IL), all digital outputs remain active. When
set to high level (V_IH), all digital output buffers are in a high impedance state while the
converter goes on sampling. When OEB is set to a low level again, the data arrives on the
output with a very short T_on delay. This feature enables the chip select of the device.
Figure 11: Timing diagram summarizes this functionality.
Reference mode control (REFMODE): this allows the internal or external settings of the
voltage references VREFP and INCM. REFMODE = 0 for internal references,
REFMODE = 1 for external references (and disables both references VREFP and INCM).
Digital outputs
Out of range (OR): this function is implemented on the output stage in order to set an "out-
of-range" flag whenever the digital data is over the full-scale range. Typically, there is a
detection of all data at ‘0’ or all data at ‘1’. It sets an output signal OR, which is in a low level
state (V_OL) when the data stays within the range, or in a high-level state (V_OH) when the
data read by the ADC is out of range.
Data ready (DR): the Data Ready output is an image of the clock being synchronized on the
output data (D0 to D13). This is a very helpful signal that simplifies the synchronization of
the measurement equipment of the controlling DSP. Like all other digital outputs, DR goes
into high impedance when OEB is set to a high level, as shown in Figure 11: Timing
diagram.
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