AIS328DQ Datasheet, PDF (30/43 Pages) STMicroelectronics – High-performance ultra low-power 3-axis accelerometer

Register description
AIS328DQ
Table 29.
ST
SIM
CTRL_REG4 description (continued)
Self-test enable. Default value: 0.
(0: self-test disabled; 1: self-test enabled)
SPI serial interface mode selection. Default value: 0.
(0: 4-wire interface; 1: 3-wire interface)
The BDU bit is used to inhibit the output register update between the reading of upper and
lower register parts. In default mode (BDU = ‘0’), the lower and upper register parts are
updated continuously. If it is not certain to read faster than output data rate, it is
recommended to set the BDU bit to ‘1’. In this way, after the reading of the lower (upper)
register part, the content of that output register is not updated until the upper (lower) part is
read also. This feature prevents the reading of LSb and MSb related to different samples.
7.6
CTRL_REG5 (24h)
Table 30. CTRL_REG5 register
0
0
0
0
0
0
TurnOn1 TurnOn0
Table 31.
TurnOn1,
TurnOn0
CTRL_REG5 description
Turn-on mode selection for sleep-to-wake function. Default value: 00.
TurnOn bits are used for turning on the sleep-to-wake function.
Table 32. Sleep-to-wake configuration
TurnOn1
TurnOn0
Sleep-to-wake status
0
0
Sleep-to-wake function is disabled
1
1
Turned on: the device is in low power mode (ODR is defined in
CTRL_REG1)
By setting TurnOn[1:0] bits to 11, the “sleep-to-wake” function is enabled. When an interrupt
event occurs, the device is switched to normal mode, increasing the ODR to the value
defined in CTRL_REG1. Although the device is in normal mode, the CTRL_REG1 content is
not automatically changed to “normal mode” configuration.
7.7
HP_FILTER_RESET (25h)
Dummy register. Reading at this address instantaneously zeroes the content of the internal
high-pass filter. If the high-pass filter is enabled, all three axes are instantaneously set to
0 g. This makes it possible to surmount the settling time of the high-pass filter.
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Doc ID 18160 Rev 3