AIS328DQ Datasheet, PDF (10/43 Pages) STMicroelectronics – High-performance ultra low-power 3-axis accelerometer

Mechanical and electrical specifications
AIS328DQ
5. Offset can be eliminated by enabling the built-in high-pass filter.
6. Typical zero-g level offset as per factory calibration @ T = 25 °C.
7. Guaranteed by design.
8. The sign of “Self-test output change” is defined by a sign bit, for all axes. Values in Table 3 are defined with the STsign bit
in the CTRL_REG4 register equal to logic “0” (positive self-test), at T = 25 °C.
9. Self-test output changes with the power supply. “Self-test output change” is defined as
OUTPUT[LSb]_{(CTRL_REG4 ST bit=1)} - OUTPUT[LSb]_{(CTRL_REG4 ST bit=0)}. 1LSb=4g/4096 at 12-bit representation, ±2 g full-
scale.
10. Output data reaches 99% of final value after 3/ODR when enabling self-test mode, due to device filtering.
2.2
Electrical characteristics
@ Vdd = 3.3 V, T = -40 °C to +105 °C unless otherwise noted^(b).
Table 4. Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Vdd Supply voltage
2.4
Vdd_IO I/O pins supply voltage⁽²⁾
1.8
Idd
Current consumption
in normal mode
2.4 V to 3.6 V
200
IddLP
Current consumption
in low-power mode
ODR=1 Hz, BW=500
Hz, T=25 °C
8
IddPdn
Current consumption in
power-down mode
0.1
VIH
Digital high level input
voltage
0.8*Vdd_IO
VIL Digital low level input voltage
VOH High level output voltage
0.9*Vdd_IO
VOL Low level output voltage
DR bit set to 00
ODR
Output data rate
in normal mode
DR bit set to 01
DR bit set to 10
DR bit set to 11
PM bit set to 010
ODR_LP
Output data rate
in low-power mode
PM bit set to 011
PM bit set to 100
PM bit set to 101
PM bit set to 110
Typ⁽¹⁾.
3.3
10
1
50
100
400
1000
0.5
1
2
5
10
Max. Unit
3.6
V
Vdd+0.1 V
450
µA
12
µA
2
µA
V
0.2*Vdd_IO V
V
0.1*Vdd_IO V
Hz
Hz
b. The product is factory calibrated at 3.3 V. Operational power supply (Vdd) over 3.6 V is not recommended.
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Doc ID 18160 Rev 3