AIS328DQ Datasheet, PDF(20/43 Page) STMicroelectronics – High-performance ultra low-power 3-axis accelerometer

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AIS328DQ Datasheet, PDF (20/43 Pages) STMicroelectronics – High-performance ultra low-power 3-axis accelerometer

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Digital interfaces

AIS328DQ

Table 13. Transfer when master is receiving (reading) one byte of data from slave

Master ST SAD + W

SUB

SR SAD + R

NMAK SP

Slave

SAK

SAK DATA

Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W

SUB

SR SAD+R

MAK

NMAK SP

Slave

SAK

SAK DATA

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number

of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit

(MSb) first. If a receiver cannot receive another complete byte of data until it has performed

some other function, it can hold the clock line SCL LOW to force the transmitter into a wait

state. Data transfer only continues when the receiver is ready for another byte and releases

the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to

receive because it is performing some real-time function) the data line must be left HIGH by

the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line

while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be

terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-

address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the

address of the first register to be read.

In the presented communication format, MAK is master acknowledge and NMAK is no

master acknowledge.

5.2

SPI bus interface

The AIS328DQ SPI is a bus slave. The SPI allows the writing and reading of the registers of

the device.

The serial interface interacts with the outside world through 4 wires: CS, SPC, SDI and

SDO.

Figure 6. Read and write protocol

SPC

SDI

SDO

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

MS AD5 AD4 AD3 AD2 AD1 AD0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

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Doc ID 18160 Rev 3

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