LSM303DLH Datasheet, PDF(24/47 Page) STMicroelectronics – Sensor module: 3-axis accelerometer and 3-axis magnetometer

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LSM303DLH Datasheet, PDF (24/47 Pages) STMicroelectronics – Sensor module: 3-axis accelerometer and 3-axis magnetometer

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Digital interfaces

LSM303DLH

7.1.1

I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After

this has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

the 8th bit tells whether the master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its address. If they match, the device considers itself addressed

by the master.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I2C embedded inside the LSM303DLH behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a slave address is sent. Once a

slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the

7 LSb represent the actual register address while the MSB enables address auto-increment.

If the MSb of the SUB field is â1â, the SUB (register address) is automatically increased to

allow multiple data read/write.

Table 11.

Master

Slave

Transfer when master is writing one byte to slave

SAD + W

SUB

DATA

SAK

Table 12. Transfer when master is writing multiple bytes to slave

Master ST SAD + W

SUB

DATA

Slave

SAK

Table 13. Transfer when master is receiving (reading) one byte of data from slave

Master ST SAD + W

SUB

SR SAD + R

NMAK SP

Slave

SAK

SAK DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number

of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit

(MSb) first. If a receiver cannot receive another complete byte of data until it has performed

some other function, it can hold the clock line SCL LOW to force the transmitter into a wait

state. Data transfer only continues when the receiver is ready for another byte and releases

the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to

receive because it is performing a real-time function) the data line must be left HIGH by the

slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line

while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be

terminated by the generation of a STOP (SP) condition.

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Doc ID 16941 Rev 1

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