TDA7505 Datasheet, PDF (21/38 Pages) STMicroelectronics – Car radio DSP for advanced signal processing

TDA7505
Electrical specifications
Figure 7. SPI clocking scheme
SS
SCK ^{(CPOL=0,CPHA=0)}
SCK ^{(CPOL=0,CPHA=1)}
SCK (CPOL=1,CPHA=0)
SCK ^{(CPOL=1,CPHA=1)}
MISO
MOSI
MSB
6
5
4
3
2
1
0
4.9
I²C Timing
Figure 8. I²C Timing
Table 15. I²C Timing
Symbol
Parameter
Test
condition
F_SCL
t_BUF
t_HD:STA
t_LOW
t_HIGH
t_SU:STA
t_HD:DAT
t_R
SCLl clock frequency
Bus free between a STOP and
Start Condition
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated start
condition
DATA hold time
Rise time of both SDA and SCL
signals
Cb in pF
Standard mode
I²C bus
Fast mode I²C bus
Unit
Min. Max.
Min.
Max.
0
100
0
400 kHz
4.7
–
1.3
–
ms
4.0
–
0.6
–
ms
4.7
–
1.3
–
ms
4.0
–
0.6
–
ms
4.7
–
0.6
–
ms
0
–
0
0.9 ms
–
1000 20+0.1Cb 300 ns
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