TDA7505 Datasheet, PDF (18/38 Pages) STMicroelectronics – Car radio DSP for advanced signal processing

Electrical specifications
4.4
SAI interface timing - receiver
Figure 3. SAI interface timing - receiver
SDI0-2
Valid
LRCKR
SCKR
(RCKP=0)
Valid
t _lrckrs
t_sdis
t_sckrl
t _lrckrh
t_sdih
t_sckrh
t_sckr
TDA7505
4.5
Table 11. SAI interface timing - receiver
Timing
Description
T_DSP(1) Internal DSP clock period (typical 1/75MHz)
t_sckr Minimum clock cycle
t_lrckrs LRCKR setup time
t_lrckrh LRCKR hold time
t_sdid SDI setup time
t_sdih SDI hold time
t_sckrh Minimum SCKR high time
t_sckrl Minimum SCKR low time
1. T_DSP = DSP master clock cycle time = 1/F_dsp
Min Typ Max Unit
13.33
ns
6 T_DSP
ns
T_DSP
ns
T_DSP
ns
T_DSP
ns
T_DSP
ns
0.35 t_sckr
ns
0.35 t_sckr
ns
SAI interface timing - transmitter
Figure 4. SAI interface timing - transmitter
SDO0-2
Valid
LRCKT
SCKT
(TCKP=0)
Valid
t _dt
t_scktl
t _lrckts
t _lrckth
t_sckth
t_sckt
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