TDA7505 Datasheet, PDF (20/38 Pages) STMicroelectronics – Car radio DSP for advanced signal processing

Electrical specifications
TDA7505
4.8
SPI interfaces (Buffered SPI, Display SPI, RDS SPI)
Figure 6. SPI interfaces
SS
V a lid
M IS O
MOSI
SCK
(C P O L= 0,C P H A = 0)
V a lid
t _setup
t_{d t r}
t_{s s s e t u p}
t_sclkl
t _hold
t_sshold
t_{s c lk h}
t_sclk
Table 14. SPI interfaces
Symbol
Description
T_DSP Internal DSP clock period (typical 1/75MHz)
Master mode
t_sclk Clock cycle
t_dtr SCK edge to MOSI valid
t_setup MISO setup time
t_hold MISO hold time
t_sclkh SCK high time
t_sclkl SCK low time
t_sssetup SS setup time
t_sshold SS hold time
Slave mode
t_sclk Clock cycle
t_dtr SCK edge to MOSI valid
t_setup MOSI setup time
t_hold MOSI hold time
t_sclkh SCK high time
t_sclkl SCK high low
t_sssetup SS setup time
t_sshold SS hold time
Min
Typ Max Unit
13.33
ns
12 T_DSP
ns
40
ns
16
ns
9
ns
0.5 t_sclk
ns
0.5 t_sclk
ns
40
ns
25
ns
12 T_DSP
ns
40
ns
16
ns
9
ns
0.5 t_sclk
ns
0.5 t_sclk
ns
40
ns
20
ns
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