STE2007_06 Datasheet, PDF (21/62 Pages) STMicroelectronics – 96 x 68 Single-chip LCD controller/driver

STE2007
Interface
4.2.1.1 Data/command transfer break
If the Host processor generates an break condition (!CS Line HIGH before having received
Bit D0) while transferring a Data byte to the Frame Memory or a Command identifier or a
command parameter, the not complete received byte is discarded, the communication is
interrupted and the interface is forced in reset state.
When !CS line becomes low again to start a new communication session STE2007 is ready
to receive the same byte interrupted re-transmitted or a new command identifier.
Figure 12. 4-lines SPI Data Transfer break condition
Break
!CS
D/!C
SCL
SDA
D7
D6
D5
D4
D3
D7
D6
D5
D4
D3
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0192
4.2.1.2 Data/command transfer pause
It is possible while transferring Frame Memory Data, Commands or Command Parameters
to insert a pause in the data transmission (!CS Line HIGH after 8 Bits Received). When !CS
is forced high after a whole byte received, the received byte is processed. Then STE2007 is
forced in a wait state ready to restart processing incoming data from the point where the
communication has been paused
If a new command identifier is transferred after a pause condition the previous
communication session is definitively closed.
Four are the possible conditions:
– Command-Pause-Command
– Command-Pause-Parameter
– Parameter-Pause-Command
– Parameter-Pause-Parameter
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