STE2007_06 Datasheet, PDF (13/62 Pages) STMicroelectronics – 96 x 68 Single-chip LCD controller/driver

STE2007
Electrical characteristics
Table 11. Input signals change time
Signal Symbol
Parameter
Inputs
tr,tf
(1)
1. To 30% & 70% levels
Min.
Typ.
Max.
Unit
10
ns
3.5
Driver TxData mode
Table 12. Timings based on 4 MHz SCLK speed
Symbol
Item
Condition
T1
Data hold time
Note 1
T2
Access time
–
T3
Output disable time
–
T4
Data setup time
–
T5
!CS pulse width high
–
Min.
100
10
25
100
250
Typ.
Max.
125
100
100
–
Units
ns
ns
ns
ns
ns
Note: 1 Data Hold Time T1 depends on SCLK high time and Max Data Hold time. It is always 3-8ns
before SCLK pulse falling edge
2 The input signal rise and fall times must be within 10ns.
3 Every timing is specified on the basis of 30% and 70% of VDDI.
Table 13. Timings based on 1 MHz SCLK speed
Symbol
Item
Condition
T1
Data hold time
–
T2
Access time
–
T3
Output disable time
–
T4
Data setup time
–
T5
1CS pulse width high
–
Min.
100
10
25
100
250
Typ.
Note: 1 The input signal rise and fall times must be within 10ns.
2 Every timing is specified on the basis of 30% and 70% of VDDI.
Max.
125
450
450
–
Units
ns
ns
ns
ns
ns
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