STM32F205VCT6TR Datasheet, PDF (20/178 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM

Functional overview
ARM
Cortex-M3
Figure 5. Multi-AHB matrix
GP
DMA1
GP
MAC _{USB OTG}
DMA2 Ethernet _HS
STM32F20xxx
S0 S1 S2
S3 S4 S5 S6 S7
M0 ^ICODE
M1 ^DCODE
M2
M3
M4
M5
M6
Bus matrix-S
Flash
memory
SRAM
112 Kbyte
SRAM
16 Kbyte
AHB1
periph
AHB2
periph
FSMC
Static MemCtl
APB1
APB2
ai15963c
3.8
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They share some centralized FIFOs for APB/AHB
peripherals, support burst transfer and are designed to provide the maximum peripheral
bandwidth (AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
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DocID15818 Rev 11