STM32F722XX Datasheet, PDF (195/229 Pages) –

STM32F722xx STM32F723xx
Electrical characteristics
Symbol
Table 108. SDRAM read timings⁽¹⁾
Parameter
Min
t_w(SDCLK)
FMC_SDCLK period
t_{su(SDCLKH _Data)}
Data input setup time
t_{h(SDCLKH_Data)}
Data input hold time
t_{d(SDCLKL_Add)}
Address valid time
t_{d(SDCLKL- SDNE)}
Chip select valid time
t_{h(SDCLKL_SDNE)}
Chip select hold time
t_{d(SDCLKL_SDNRAS)}
SDNRAS valid time
t_{h(SDCLKL_SDNRAS)}
SDNRAS hold time
t_{d(SDCLKL_SDNCAS)}
SDNCAS valid time
t_{h(SDCLKL_SDNCAS)}
SDNCAS hold time
1. Guaranteed by characterization results.
2Thclk -0.5
1.5
2
-
-
0.5
-
0.5
-
0
Max
2Thclk +0.5
-
-
1.5
1.5
-
1
-
1.5
-
Symbol
Table 109. LPSDR SDRAM read timings⁽¹⁾
Parameter
Min
Max
t_W(SDCLK)
FMC_SDCLK period
t_{su(SDCLKH_Data)}
Data input setup time
t_{h(SDCLKH_Data)}
Data input hold time
t_{d(SDCLKL_Add)}
Address valid time
t_{d(SDCLKL_SDNE)}
Chip select valid time
t_{h(SDCLKL_SDNE)}
Chip select hold time
t_{d(SDCLKL_SDNRAS}
SDNRAS valid time
t_{h(SDCLKL_SDNRAS)}
SDNRAS hold time
t_{d(SDCLKL_SDNCAS)}
SDNCAS valid time
t_{h(SDCLKL_SDNCAS)}
SDNCAS hold time
1. Guaranteed by characterization results.
2Thclk -0.5
0
4.5
-
-
0
-
0
-
0
2Thclk +0.5
-
-
1.5
1.5
-
0.5
-
1.5
-
Unit
ns
Unit
ns
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