STM32F722XX Datasheet, PDF (139/229 Pages) –

STM32F722xx STM32F723xx
Electrical characteristics
Table 46. PLLI2S characteristics (continued)
Symbol
Parameter
Conditions
Min Typ
Jitter⁽³⁾
Master I2S clock jitter
Cycle to cycle at
RMS
-
12.288 MHz on
48KHz period,
N=432, R=5
peak
to
-
peak
Average frequency of
12.288 MHz
N = 432, R = 5
-
on 1000 samples
90
±280
90
WS I2S clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
-
400
I_{DD(PLLI2S)(4)}
PLLI2S power consumption on
V_DD
I_{DDA(PLLI2S)(4)}
PLLI2S power consumption on
V_DDA
VCO freq = 100 MHz
VCO freq = 432 MHz
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.30
0.55
-
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
Max
-
-
-
-
0.40
0.75
0.40
0.85
Unit
ps
ps
ps
mA
mA
Table 47. PLLISAI characteristics
Symbol
Parameter
Conditions
Min
f_{PLLSAI_IN}
f_{PLLSAIP_OUT}
PLLSAI input clock⁽¹⁾
PLLSAI multiplier output clock
for 48 MHz
-
0.95⁽²⁾
-
-
f_{PLLSAIQ_OUT}
PLLSAI multiplier output clock
for SAI
-
-
f_{VCO_OUT}
t_LOCK
PLLSAI VCO output
PLLSAI lock time
-
100
VCO freq = 100 MHz
75
VCO freq = 432 MHz
100
Jitter⁽³⁾
Master SAI clock jitter
Cycle to cycle at
RMS
-
12.288 MHz on
48KHz period,
N=432, R=5
peak
to
-
peak
Average frequency of
12.288 MHz
N = 432, R = 5
-
on 1000 samples
FS clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
-
Typ
1
48
-
-
-
-
90
± 280
90
400
Max
2.10
75
216
432
200
300
-
-
-
-
Unit
MHz
µs
ps
ps
ps
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